1. Field of the Invention
The present invention relates to an image data transfer controller.
2. Description of the Prior Art
Examples of an image forming apparatus such as a facsimile include one comprising a CPU (Central Processing Unit) which is a main control unit and the other control unit such as an image processing unit to be a bus master. In such an image forming apparatus, image data stored in a memory is subjected to image processing by the image processing unit, and the image data after the image processing is stored in the other memory. As data transfer between the memory and the control unit such as the image processing unit, DMA (Direct Memory Access) is generally used so as to perform transfer at high speed.
Examples of conventional DMA transfer include burst transfer in which transfer is continuously performed until a required number of image data are transferred after a right to control a bus is acquired, as shown in FIG. 4, or a cycle steal transfer in which a right to control a bus is acquired for each transfer and transfer is performed every time the right to control a bus is acquired, as shown in FIG. 5.
In FIGS. 4 and 5, a bus request signal *BR is a request to release a bus which is inputted to a CPU which is a main control unit of a facsimile from the other control unit such as an image processing unit. If the other control unit desires to use the bus, this signal is asserted. A bus grant signal *BG is a signal asserted by the CPU so as to inform, when the CPU releases the bus on the basis of the bus request signal *BR, the other control unit of the release.
A bus grant acknowledge signal *BGACK is a signal asserted by the other control unit when the other control unit issuing the request to release a bus knows that the bus is released by the bus grant signal *BG. The other control unit becomes a bus master while asserting the bus grant acknowledge signal *BGACK.
In the burst transfer, the CPU and the other device cannot use a CPU bus during a transfer period. When another important processing occurs, therefore, the processing cannot be performed, resulting in an inferior operation.
On the other hand, in the cycle steal transfer, an operation for acquiring the right to control a bus is frequently performed, whereby it takes longer to transfer all data.